Semiconductor device and method for its preparation

ABSTRACT

An improved means and method for isolating semiconductor devices on a semiconductor substrate, comprising a shallow region formed between the semiconductor substrate and an epitaxial layer of each device, and between a buried layer of each device and an isolation region separating adjacent devices. The shallow region has conductivity type opposite to that of the semiconductor substrate and higher impurity concentration than that of the epitaxial layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device and to a method for itspreparation. More particularly, this invention relates to asemiconductor device with improved breakdown voltage and integrationdensity, and to a method for its preparation.

2. Description of the Prior Art

Generally, in a bipolar semiconductor device, isolation is necessary toseparate electrically between elements, and various techniques for thispurpose have been offered.

As one example of such techniques, V-groove isolation withpolycrystalline silicon (VIP) is a well known method. This methodutilizes a V-shaped groove as an isolation region between elements inthe bipolar semiconductor device. The VIP method is explained in detailin the following description and is very important with respect to thepresent invention. To illustrate the prior art semiconductor device andmethod for manufacturing the same, reference is made to FIGS. 1-12.

FIG. 1 shows a partial cross-section of a P type silicon semiconductorsubstrate 10. In FIG. 1, after forming an oxide film 12 over the entiresurface of the P type silicon semiconductor substrate 10 and selectivelyforming windows 14, 16 by patterning the oxide film 12, impurities arediffused through the windows 14, 16; and thereby the N+ type buriedlayers 18, 20 are formed in the surface of the semiconductor substrate10.

Referring to FIG. 2, after removing the oxide film 12, an N- typesilicon semiconductor layer 22 is formed over the entire area of theburied layers 18, 20 and the semiconductor substrate 10 by epitaxialgrowth. Here, the Miller indices of the semiconductor substrate 10 are(100), the depth of the buried layers 18, 20 is about 3 to 5 microns andthe thickness of the epitaxial layer 22 is about 2 to 3 microns.

Referring to FIG. 3, an oxide film 24 and a silicon niride film 26 areformed on the epitaxial layer 22 by oxidation and SiN deposition,respectively. Then the silicon nitride film 26 and the oxide film 24 aresubject to patterning and thereby the windows 28, 30, 32 are formed.

Referring to FIG. 4, V-shape etching is performed in the epitaxial layer22 and the semiconductor substrate 10 by using the patterned siliconnitride film 24 as a mask, thereby V-shaped grooves (isolation regions)29, 31, 33 can be formed. Here, as an etching solution, an anisotropicetching solution such as potassium hydroxide (KOH) solution withisopropyl alcohol or ethylene diamine with pyrocatechol is used.

Referring to FIG. 5, oxide films 34, 36, 38 are formed in the V-shapegrooves 29, 31, 33 by oxidation.

Referring to FIG. 6, the polycrystalline silicon film 40 is formed onthe entire surface of the device by chemical vapor deposition (CVD). Thethickness of the polycrystalline silicon film 40 should be at least suchthat the V-shape grooves 29, 31, 33 are sufficiently buried.

Referring to FIG. 7, the surface of the device is polished so that thepolycrystalline silicon films 40 remain only within the V-shape grooves29, 31, 33.

Referring to FIG. 8, oxide films 42, 44, 46 are formed in the surface ofthe remaining polycrystalline silicon films 40 by oxidation. Thereby,the polycrystalline silicon films 40 are totally buried within the oxidefilms.

Referring to FIG. 9, the silicon nitride film 26 is removed by etching,for instance, using phosphoric acid (H₃ PO₄). In FIG. 9, the oxide filmis represented by the numeral 24.

Referring to FIG. 10, P type base regions 48, 50 are formed by ionimplantation using, for example, a photoresist as a mask. Here, itshould be understood that a diffusion method may also be employed toform the P type base regions 48, 50 as is well known in the prior art.

Referring to FIG. 11, collector electrode windows 52, 62 and emitterelectrode windows 56, 58 are formed by patterning the oxide film 24.Then, impurities are diffused through these windows, whereby N+ typecollector contact regions 64, 70 and N+ type emitter regions 66, 68 areformed. Thereafter, base electrode windows 54, 60 are formed bypatterning the oxide film 24.

Referring to FIG. 12, an aluminum electrode material 72 is evaporated onthe entire surface of the device. Then, the aluminum 72 is selectivelyremoved to define a conductor wiring area. Phosphoric acid with anadditive of nitric acid may be used for etching the aluminum.

In a semiconductor device as mentioned above, the semiconductor layer 22formed by the epitaxial growth was relatively thick. However, morerecently, such epitaxial layer 22 must be thin because the width of theisolation regions 29, 31, 33 is narrowed so as to obtain highintegration density. Usually, the depth of the V-shape groove isdetermined as about 0.7× width of the isolation region.

As can be seen in FIG. 10, a PNP configuration is formed by the P typebase region 48 (50), the N- type epitaxial layer 22 and the P typesemiconductor substrate 10. Therefore, when the epitaxial layer 22becomes thin, the base region 48 (50) and the semiconductor substrate 10are likely to suffer punch through.

As a method for avoiding such punch through, the N type impurityconcentration of the epitaxial layer 22 can be increased. However, inthis case, the depletion layer between the base and the collectorbecomes narrow, and accordingly the capacitance between the base and thecollector increases. Therefore, it is not desirable to increase the Ntype impurity concentration of the epitaxial layer 22 when a high speedtransistor is desired.

FIG. 13 shows another example of the prior art bipolar semiconductordevice. In FIG. 13, the configuration of the isoplanar type bipolarsemiconductor device which has an isolation region 76 comprising, forexample, silicon dioxide is disclosed. In FIG. 13, the same referencenumerals as that of FIGS. 1 to 13 indicate the same portions.

In this example, the generation of punch through between the base region48 (50) and the semiconductor substrate 10 is prevented since the N+type buried layer 18 (20) makes contact with the isolation region. Inorder to employ such configuration, the isolation region 76 must be wideand, therefore, it is difficult to obtain high integration density. Ofcourse, it is impossible to employ such method, i.e., making the N+buried layer contact with the isolation region, in the case of the abovementioned VIP method. This prior art method is therefore not useful toisolate between elements.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicewhich can prevent punch through, and to provide a simple method forpreparation of the semiconductor device.

Another object of the present invention is to provide a semiconductordevice which has a narrow isolation region, and to provide a simplemethod for preparation of the semiconductor device.

A further object of the present invention is to provide a semiconductordevice which can be prevented from generation of punch through even whenan epitaxial layer comprising a portion of the device is thin, and toprovide a simple method for the preparation of the semiconductor device.

Still another object of the present invention is to provide asemiconductor device which can be prevented from generation of punchthrough even when the impurity concentration of the epitaxial layercomprising a portion of the device is low, and to provide a simplemethod for preparation of the semiconductor device.

The above-mentioned objects can be accomplished by the semiconductordevice of the present invention which comprises (a) a semiconductorsubstrate having a first conductivity type, (b) a plurality of buriedlayers of a second conductivity type opposite to the first conductivitytype selectively formed in the surface of the semiconductor substrate,(c) an epitaxial layer of the second conductivity type formed over thesemiconductor substrate and the buried layer, (d) a plurality of regionsof the first conductivity type formed in the epitaxial layer, (e) aplurality of isolation regions formed between the buried layers, theisolation regions extending downwardly from the surface of the epitaxiallayer to the semiconductor substrate, and (f) a plurality of regions ofthe second conductivity type formed between the semiconductor substrateand the epitaxial layer, and between the isolation regions and theburied layers, the second conductivity type regions having higherimpurity concentration than that of said epitaxial layer.

The above-mentioned semiconductor device can be prepared by the methodof the present invention, which comprises the steps of (a) selectivelyforming a plurality of the layers of a second conductivity type in asemiconductor substrate surface of a first conductivity type, (b)forming the regions of the second conductivity type in the semiconductorsubstrate surface between the second conductivity type layers, (c)forming the epitaxial layer of the second conductivity type over theentire area of the second conductivity type region and the secondconductivity type layers, the epitaxial layer having lower impurityconcentration than that of the second conductivity type region.

Additional objects and features of the present invention will appearfrom the following description in which the preferred embodiment of theinvention have been set forth in detail in conjunction with thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 12 show the cross-sections during manufacturing steps of aprior art bipolar semiconductor device utilizing the VIP method.

FIG. 13 shows the cross-section of another prior art bipolarsemiconductor device utilizing the isoplanar method.

FIGS. 14 to 17 show the cross-sections during manufacturing steps of asemiconductor device according to the present invention.

FIGS. 18 to 21 show the cross-section during manufacturing steps ofanother semiconductor device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 14 to 17 show the cross-sections during manufacturing steps of asemiconductor device according to an embodiment of the presentinvention. The semiconductor device in accordance with the presentinvention comprises N type layers formed between semiconductor substrateand the epitaxial layer, and between the isolation regions and theburied layers, as compared with the prior art semiconductor deviceexplained with reference to FIGS. 1 to 12. The method for preparation ofthe semiconductor device in accordance with the present inventioncomprises the step of forming N type layers in the semiconductorsubstrate surface between the buried layers prior to the step of formingthe epitaxial layer as compared with the prior art method explained withreference to FIGS. 1 to 12.

As an N type impurity used in this step, arsenic (As) or anitmony (Sb)are preferably since they have small diffusion coefficients, and therebythe N type layer can be formed shallowly. As a method for forming the Ntype layer, it is preferable to employ an ion implantation method ratherthan a diffusion method since it is possible to form a more shallow Ntype of layer by implantation.

FIG. 14 shows a partial cross-section of a P type silicon semiconductorsubstrate 10. In a similar way as explained with reference to FIG. 1,after forming an oxide film over the entire surface of the P typesilicon semiconductor substrate 10 and selectively forming windows bypatterning the oxide film, impurities are diffused through the windows,thereby N+ type buried layers 18, 20 are formed in the surface of thesemiconductor substrate 10. Then, after removing the oxide film an Ntype impurity such as arsenic or antimony is introduced into the surfaceof the semiconductor substrate 10. Thereby, an N type shallow layer 80is formed in the semiconductor substrate surface between the buriedlayers 18, 20. It is preferable to employ an ion implantation method inintroducing the N type impurity in the surface of the semiconductorsubstrate 10 so as to get a thin layer, and in this case, the N typeimpurity can be introduced in the entire surface of the semiconductorsubstrate 10. Although the N type impurity is also introduced in theburied layers 18, 20 the buried layers 18, 20 will remain N+ type. Inthis step, a diffusion method may also be employed to introduce the Ntype impurity into the surface of the semiconductor substrate 10.

Referring then to FIG. 14, an N- type silicon semiconductor layer 22 isformed over the entire area of the N type layer 80 and the N+ typeburied layers 18, 20 by epitaxial growth. After forming the epitaxiallayer 22, the processes for preparing a bipolar semiconductor device arethe same as the conventional method explained with reference to FIGS. 3to 12.

FIG. 16 corresponds to FIG. 9, and the configuration of FIG. 16 is thesame as that of FIG. 9 except that FIG. 16 comprises the N type layer80.

In the same way, FIG. 17 corresponds to FIG. 12, and the configurationof FIG. 17 is the same as that of FIG. 12 except that FIG. 17 comprisesthe N type layer 80. In FIGS. 14 to 17, the same portions as thoseexplained with reference to FIGS. 1 to 12 are given the same referencenumerals. In this embodiment, the punch through voltage between the baseregions 48, 50 and the semiconductor substrate 10 can be controlled byselecting the impurity concentration of the N type layer 80. Theimpurity concentration of the N type layer 80 must be higher than thatof the epitaxial layer 22. However, if the impurity concentration of theN type layer 80 is too high, it will be difficult to obtain isolationbetween elements. In other words, in such case, the layer 80 will becomedeep after heat treatment of the epitaxial growth to form thesemiconductor layer 22. It is preferable that the depth of the N typelayer 80 be 0.5 microns, or less, when the thickness of the epitaxiallayer 22 is 2 to 3 microns.

FIGS. 18 to 21 show the cross-sections during manufacturing steps of asemiconductor device according to another embodiment of the presentinvention. The semiconductor device in accordance with this embodimentfurther comprises P type layers formed between the semiconductorsubstrate and the N type layers, and between the isolation region andthe buried layers as compared with the embodiment as explained withreference to FIGS. 14 to 17.

This configuration is recommended if it is difficult to realizeisolation between elements from the relation of the depth of the N typelayer 80 or the thickness of the epitaxial layer 22 and the depth of theV-shaped groove isolation region in case of the embodiment as explainedwith reference to FIGS. 14 to 17.

This configuration is extremely effective in the case where the impurityconcentration of the semiconductor substrate cannot be made high inorder to reduce parasitic capacitance, In other words, when the impurityconcentration of the semiconductor substrate is low, an N type channelis likely to be generated in the semiconductor substrate along theV-shaped groove isolation region. Therefore, it will be difficult to getisolation between elements. The method for preparation of thesemiconductor device in accordance with this embodiment furthercomprises the step of forming a P type layer in the semiconductorsubstrate between the buried layers prior to the step of forming the Ntype layer as compared with the method as explained with reference toFIGS. 14 to 17.

FIG. 18 shows a partial cross-section of a P- type silicon semiconductorsubstrate 10'. The impurity concentration of the semiconductor substrate10' is shown as P- for representing the case where the impurityconcentration is low. In a similar way as explained with reference toFIG. 1, after forming an oxide film over the entire surface of the P-type silicon semiconductor substrate 10' and selectively forming windowsby patterning the oxide film, impurities are diffused through thewindows, thereby N+ type buried layers 18, 20 are formed in the surfaceof the semiconductor substrate 10'. Then, after removing the oxide film,a P type impurity such as boron is introduced in the surface of thesemiconductor substrate 10'.

It is preferable to employ an ion implantation method in introducing theP type impurity in the surface of the semiconductor substrate 10' so asto get a thin layer, and in this case, the P type impurity can beintroduced in the entire surface of the semiconductor substrate 10'.Thereby a P type layer 82 is formed in the semiconductor substratesurface between the buried layers 18, 20. The impurity concentration ofthe P type layer 82 must be higher than that of the semiconductorsubstrate 10', so as to prevent the formation of an N type channel inthe semiconductor substrate 10' along an isolation region as explainedbefore. Then, an N type impurity such as arsenic or antimony isintroduced in the surface of the semiconductor substrate 10'.

It is also preferable to employ an ion implantation method inintroducing the N type impurity. Thereby an N type shallow layer 84 isformed in the semiconductor substrate surface between the buried layers18, 20. The impurity concentration of the N type layer 84 must be higherthan that of the epitaxial layer 22 as shown in FIG. 19. After formingthe N type shallow layer 84, processes for preparing a bipolarsemiconductor device are the same as the method explained with referenceto FIGS. 14 to 17.

FIG. 19 corresponds to FIG. 14, and the configuration of FIG. 19 is thesame as that of FIG. 15 except that FIG. 19 comprises the P type layer82.

In the same way, FIGS. 20 and 21 correspond to FIGS. 16 and 17,respectively.

The practical data for this embodiment will be indicated as follows.

Impurity concentration of the semiconductor substrate 10': 1×10¹⁶atom/cm³ or less

Impurity concentration of the buried layers 18, 20:

3×10¹⁹ to 5×10¹⁹ atom/cm³

Dose amount of the P type layer 82: 5×10¹² to 5×10¹³ atom/cm²(Acceleration voltage: 100 to 200 KeV)

Dose amounts of the N type layer 84: 1×10¹³ to 15×10¹³ atom/cm²(Acceleration voltage: 50 to 150 KeV)

Thickness of the epitaxial layer 22: 2 microns or less Depth of the baseregions 48, 50: 0.5 microns or less Depth of the V-shape groove: 2.1microns

Maximum width of the isolation region: 3 microns or less

As has been described, according to the present invention it is possibleto provide a semiconductor device which can avoid punch through evenwhen the isolation region is designed to be narrow in order to obtainhigh integration density. It will be apparent that many modificationsand variations may be effected without departing from the scope of thenovel concepts of the present invention; it is intended by the appendedclaims to cover such modifications and adaptations which fall within thetrue spirit and scope of the present invention.

what is claimed is:
 1. A semiconductor device comprising:a semiconductorsubstrate having a first conductivity type; a plurality of buried layersof a second conductivity type opposite to said first type formed inselected portions of the surface of said semiconductor substrate anepitaxial layer of said second conductivity type formed over saidsemiconductor substrate and said layers; a plurality of isolationregions formed between adjacent ones of said buried layers, saidisolation regions extending downward from the surface of said epitaxiallayer to said semiconductor substrate; an epitaxial layer of said secondconductivity type formed over said semiconductor substrate and saidburied layers; a plurality of first regions having said firstconductivity type formed in said epitaxial layer corresponding to saidburied layers, each said first region extending to respectively contactsaid isolation regions; and a plurality of second regions having saidsecond conductivity type formed between said semiconductor substrate andsaid epitaxial layer, and between said isolation regions and said buriedlayers, said second conductivity type regions having higher conductivitythan that of said epitaxial layer and have a depth shallower than thedeepest portion of the buried layers.
 2. The device of claim 1,comprising a plurality of third regions of said first conductivity typeformed between said second regions and said semiconductor substrate, andbetween said isolation regions and said buried layers, said thirdregions having higher conductivity than that of said semiconductorsubstrate.
 3. The device of claim 1 or 2, wherein said conductivity ofsaid second regions is lower than that of said buried layers.
 4. Thedevice of claim 1 or 2, wherein said semiconductor substrate is silicon.5. The device of claim 1 or 2, wherein said epitaxial layer is silicon.6. The device of claim 1 or 2, wherein said isolation regions comprise aV-shaped groove filled with a material comprising polycrystallinesilicon.
 7. The device of claims 1 or 2, said first regions having adepth of 0.5 microns or less.
 8. The device of claim 1 or 2, saidisolation regions having a width of 3 microns or less.
 9. The device ofclaims 1 or 2, said isolation regions having a width of 3 microns orless and a depth of approximately 2 microns or less, and said firstregions having a depth of 0.5 microns or less.
 10. The device of claims1 or 2, said isolation regions comprising a V-shape with a width of 3microns or less and a depth of 0.7 times the width.